System Clock Control Register (Sycc) - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 3 CPU
3.6.3

System Clock Control Register (SYCC)

The system clock control register (SYCC) manages clock settings such as selection of
the clock speed and oscillation stabilization wait time.
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Configuration of the System Clock Control Register (SYCC)
Figure 3.6-5 Configuration of System Clock Control Register (SYCC)
Address
bit7
0007
SCM
H
R
R/W : Readable/Writable
R : Read only
: Unused
M : Mask option
: Initial value
56
bit6 bit5 bit4 bit3 bit2
WT1 WT0
R/W R/W
bit1 bit0
Initial value
CS0 1--MM-00
CS1
B
R/W R/W
Clock speed selection bits
CS1 CS0
Instruction cycle (when F
(5.12 µs)
0 0 64/F
CH
(1.28 µs)
0 1 16/F
CH
(0.64 µs)
1 0 8/F
CH
(0.32 µs)
1 1 4/F
CH
Oscillation stabilization wait time selection bits
WT1 WT0
Oscillation stabilization wait time according to
output of the time-base timer (when F
0 0 Setting prohibited
14
Approx. 2 /F
0 1
17
Approx. 2 /F
1 0
18
Approx. 2 /F
1 1
CH
System clock monitor bit
SCM
0 Clock stopping or waiting for stabilization of oscillation
Active mode
1
is 12.5 MHz)
CH
is 12.5 MHz)
CH
(approx. 1.31 ms)
CH
(approx. 10.5 ms)
CH
(approx. 21.0 ms)