Control Status Register (Tmcsr); Table 12.2-1 Csl Bit Setting Clock Source - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 12 16-BIT RELOAD TIMER

12.2 Control Status Register (TMCSR)

The control status register is used to control the 16-bit timer operation mode and
interrupts.
Set the bits other than UF, CNTE, and TRG again when CNTE is 0.
Simultaneous writing is enabled.
Configuration of Control Status Register (TMCSR)
The configuration of the control status register (TMCSR) is shown below:
11
TMCSR
Address:00002E CSL1
H
000036
H
000042 R/W
H
Bit Functions of Control Status Register (TMCSR)
[bits 11, 10] CSL1, CSL0 (Count clock SLect)
These bits are used to select the count clock.
Table 12.2-1 lists the clock sources that can be selected.

Table 12.2-1 CSL Bit Setting Clock Source

CSL1
[bits 9, 8, 7] MOD2, MOD1, MOD0 (MODe)
These bits specify the operation mode.
Always set these bits to "0".
[bit 6] OUTE (OUTput Enable)
Always set this bit to "0".
[bit 5] OUTL
Always set this bit to "0".
[bit 4] RELD
This is a reload enable bit. Setting this bit to "1" enables the reload mode. When the
counter value underflows from 0000
register is loaded to the counter and the counter continues counting. When the counter
value underflows 0000
284
10 9 8
CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
R/W R/W R/W
CSL0
0 0
0 1
1 0
1 1
to FFFF
H
7 6 5 4
R/W R/W R/W R/W
Clock source (
Reserved
to FFFF
H H
while the bit is "0", the counter stops counting.
H
3 2 1
UF CNTE
R/W R/W R/W
machine clock)
1
/2
3
/2
5
/2
in reload mode, the value in the reload
0
Initial value
TRG
-000
H
R/W