16.13 Operating Description Of Input Capture Function - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 16 8/16-BIT COMPOSITE TIMER

16.13 Operating Description of Input Capture Function

This section describes the operations of the input capture function for the 8/16-bit
composite timer.
Operation of Input Capture Function
The composite timer requires the settings shown in Figure 16.13-1 to serve as the input capture function.
T00/01CR0
T00/01CR1
TMCR
T00/01DR
When the input capture function is selected, the counter value is stored to the 8/16-bit composite timer
00/01 data register (T00DR/T01DR) upon detection of an edge of the external signal input. The edge to be
detected is selected by timer operation mode setting (T00CR0/T01CR0:F3, F2, F1, F0).
This function is available in either free-run mode or clear mode, which can be selected by timer operation
mode setting.
In clear mode, the counter starts counting from "00
transferred to the 8/16-bit composite timer 00/01 data register (T00DR/T01DR), the interrupt flag
(T00CR1/T01CR1:IR) is set to "1", and the counter continues to count by restarting at "00
When the edge is detected in free-run mode, the counter value is transferred to the 8/16-bit composite timer
00/01 data register (T00DR/T01DR) and the interrupt flag (T00CR1/T01CR1:IR) is set to "1". In this case,
the counter continues to count without being cleared.
This function has no effect on the buffer full flag (T00CR1/T01CR1:BF).
To measure the time exceeding the length of the counter, software can be used to count the number of
occurrences of a counter overflow. When the counter causes an overflow, the interrupt flag (T00CR1/
T01CR1:IF) is set to "1". The interrupt service routine can therefore be used to count the number of times
the overflow occurs.
The capture value in the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) must be nullified if
an interrupt occurs before the timer is activated (before "1" is written to the STA bit).
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Figure 16.13-1 Settings for Input Capture Function
bit7 bit6 bit5
IFE C2 C1
STA HO IE
1
TO1 TO0 IIS
× ×
Holds pulse width measurement value
: Used bit
×: Unused bit
1: Set "1"
0: Set "0"
bit4 bit3 bit2
C0 F3 F2
IR BF IF
×
MOD FE11 FE10
". When the edge is detected, the counter value is
H
bit1 bit0
F1 F0
SO OE
× ×
FE01 FE00
".
H