Table of Contents
Advertisement
Chapter 16 Clock Supervisor
3.Block Diagram Clock Supervisor
3. Block Diagram Clock Supervisor
This section presents a block diagram of the Clock Supervisor. The building blocks of the Clock
Supervisor are:
l Main Clock Supervisor
l Sub-Clock Supervisor
l Control Logic
l RC-Oscillator
■ Block Diagram Clock Supervisor
EXT_RST
PONR
OSC_STAB
MCLK
MCLK_STBY
SCLK
SCLK_STBY
Remark: SCLK_OUT and MCLK_OUT can be observed using the Clock Monitor Module. SCLK_MISSING and
MCLK_MISSING can be programmed to device specific outputs (see the datasheet of the used device for the infor-
mation which pins are used) by setting OUTE=1.
224
Figure 3-1 Bock Diagram Clock Supervisor
Clock Supervisor
Control Logic
ERSX
PONR
Clock Supervisor Control Register
TB_ST
7
6
SCKS
MM
SM
RC_CLK
Timeout Counter
CLK
RC_CLK
RC_CLK
Internal Bus
ERSXO
CSVCR
5
4
3
2
1
0
RCE
MSVE SSVE SRST
OUTE
RCE
SM
SCKS
MM
TO_MCLK
TO_SCLK
Main Clock
Supervisor
MCLK
NO_MCLK
EN
STBY
RC_CLK
Sub-Clock
Supervisor
SCLK
NO_SCLK
EN
STBY
RC_CLK
EXT_RST_OUT
OUTE
RC-Oscillator
RC_CLK
STBY RC_CLK
SCLK_MISSING
MCLK_MISSING
OR
S
0
MCLK_OUT
MUX
1
S
0
SCLK_OUT
MUX
1
Advertisement
Table of Contents
