Section 5 Resets And Interrupts; Overview; Vectors; Vector Table - Motorola MC9S12DT256 User Manual

Section 5 Resets and Interrupts

5.1 Overview

Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.

5.2 Vectors

5.2.1 Vector Table

Table 5-1 lists interrupt sources and vectors in default order of priority.
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3

Table 5-1 Interrupt Vector Locations

Interrupt Source
Reset
Clock Monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real Time Interrupt
Enhanced Capture Timer channel 0
Enhanced Capture Timer channel 1
Enhanced Capture Timer channel 2
Enhanced Capture Timer channel 3
Enhanced Capture Timer channel 4
Enhanced Capture Timer channel 5
Enhanced Capture Timer channel 6
Enhanced Capture Timer channel 7
Enhanced Capture Timer overflow
Pulse accumulator A overflow
Pulse accumulator input edge
SPI0
SCI0
SCI1
ATD0
MC9S12DT256 Device User Guide — V03.07
CCR
Local Enable
Mask
None None
None PLLCTL (CME, SCME)
None COP rate select
None None
None None
X-Bit None
I-Bit IRQCR (IRQEN)
I-Bit CRGINT (RTIE)
I-Bit TIE (C0I)
I-Bit TIE (C1I)
I-Bit TIE (C2I)
I-Bit TIE (C3I)
I-Bit TIE (C4I)
I-Bit TIE (C5I)
I-Bit TIE (C6I)
I-Bit TIE (C7I)
I-Bit TSRC2 (TOF)
I-Bit PACTL (PAOVI)
I-Bit PACTL (PAI)
I-Bit SP0CR1 (SPIE, SPTIE)
SC0CR2
I-Bit
(TIE, TCIE, RIE, ILIE)
SC1CR2
I-Bit
(TIE, TCIE, RIE, ILIE)
I-Bit ATD0CTL2 (ASCIE)
HPRIO Value
to Elevate
–
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
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