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Processor Register Description
31
2.2.1.5
Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for
results generated by processor operations. Bit 4, the extend bit (X bit), is also used as an
input operand during multiprecision arithmetic computations.
Bits
Name
4
3
2
1
0
2-4
15
15
Figure 2-2. User Programming Model
4
3
X
N
Figure 2-3. Condition Code Register (CCR)
Table 2-1. CCR Field Descriptions
X
Extend condition code bit.
N
Negative condition code bit. Set if the most significant bit of the result is set;
otherwise cleared.
Z
Zero condition code bit. Set if the result equals zero; otherwise cleared.
V
Overflow condition code bit. Set if an arithmetic overflow occurs implying that the
result cannot be represented in the operand size; otherwise cleared.
C
Carry condition code bit. Set if a carry out of the operand msb occurs for an
addition, or if a borrow occurs in a subtraction; otherwise cleared
Set to the value of the C bit for arithmetic operations; otherwise not affected.
MCF5282 User's Manual
7
0
D0
D1
D2
DATA
D3
REGISTERS
D4
D5
D6
D7
A0
A1
A2
ADDRESS
A3
REGISTERS
A4
A5
A6
USERSTACK
A7
POINTER
PROGRAM
PC
COUNTER
7
0
CONDITION
CCR
CODE
REGISTER
2
1
0
Z
V
C
Description
MOTOROLA
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