Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2433

Sharc+ processor
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ADSP-SC58x EMAC Register Descriptions
Time Stamp High Second Register
The
EMAC_TM_HISEC
Figure 31-170: EMAC_TM_HISEC Register Diagram
Table 31-202: EMAC_TM_HISEC Register Fields
Bit No.
(Access)
15:0
TSHWR
(R/W)
31–342
register contains the upper 32 bits of the seconds field of the system time.
15
14
13
0
0
0
TSHWR (R/W)
Time Stamp Higher Word Seconds
Register
31
30
29
0
0
0
Bit Name
Time Stamp Higher Word Seconds Register.
The EMAC_TM_HISEC.TSHWR bit field contains the most significant 16-bits of the
time stamp seconds value. The register is directly written to initialize the value. This
register is incremented when there is an overflow from the 32-bits of the
EMAC_TM_SEC
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
register.
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0

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