Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2327

ADSP-SC58x EMAC Register Descriptions
Interrupt Status Register
The register indicates EMAC interrupt status.
EMAC_ISTAT
LPIIS (R)
LPI Interrupt Status
TS (R)
Time Stamp Interrupt Status
MMCRC (R)
MMC Receive Checksum Offload Interrupt
Status
MMCTX (R)
MMC Transmit Interrupt Status
Figure 31-93: EMAC_ISTAT Register Diagram
Table 31-125: EMAC_ISTAT Register Fields
Bit No.
(Access)
10 LPIIS
(R/NW)
9 TS
(R/NW)
7 MMCRC
(R/NW)
6 MMCTX
(R/NW)
31–236
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
LPI Interrupt Status.
The EMAC_ISTAT.LPIIS bit is set for any LPI state entry or exit in the MAC
Transmitter or Receiver.
Time Stamp Interrupt Status.
The EMAC_ISTAT.TS bit is set when:
There is an overflow in the
The EMAC_TM_STMPSTAT.ATSTS bit is asserted.
The EMAC_ISTAT.TS bit is cleared on reading the byte 0 of the
EMAC_TM_STMPSTAT
MMC Receive Checksum Offload Interrupt Status.
The EMAC_ISTAT.MMCRC bit is set high whenever an interrupt is generated in the
EMAC_IPC_RXINT. This bit is cleared when all the bits in this interrupt register are
cleared.
MMC Transmit Interrupt Status.
The EMAC_ISTAT.MMCTX bit is set high whenever an interrupt is generated in the
EMAC_MMC_TXINT
ister are cleared.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
EMAC_TM_SEC
register.
register. This bit is cleared when all the bits in this interrupt reg-
RGMIIIS (R)
RGMII or SMII Interrupt Status
MMC (R)
MMC Interrupt Status
MMCRX (R)
MMC Receive Interrupt Status
register, or