Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2557

I/O Pin Buffers
Pin Buffer Signals
The pin buffer is based on three signals shown in the Pin Buffer Example figure and described in the following
sections.
Figure 33-4: Pin Buffer Example
Pin Buffer Input Signal
A pin buffer input (DAIn_PBxx_I) is driven as an output from the processor when the pin buffer enable is set
(=1). Each physical pin (connected to a bonded pad) can be connected through the SRU to any of the outputs of the
DAI peripherals, based on the bit field values. The SRU can also be used to route signals that control the pins in
other ways. Many signals can be configured for use as control signals.
Pin Buffer Enable Signal
When a pin buffer enable (DAIn_PBENxx_I) is set (=1), the signal present at the corresponding pin buffer input
(DAIn_PBxx_I) is driven off-chip as an output. When a pin buffer enable is cleared (=0), the signal present at the
corresponding pin buffer input is ignored. The pin enable control registers activate the drive buffer for each of the
DAI pins. When the pins are not enabled (driven), they can be used as inputs. There are two options to control the
pin buffer enable signal; setting the level high for a static solution, or connecting the dedicated peripheral's pin buf-
fer output enable signal to its pin buffer, which automatically enables the pin buffer.
Pin Buffer Input Level State
The DAI pads are provided with an input enable signal (IE). The signal is used to ensure that the input path
(DAI_PBxx_O) is pushed to a known state (versus a floating state in case of no external drivers on the DAI pad).
This state can be considered as an AND gate of the pad signal with the IE as shown in the pin buffer figure. The IE
signal is controlled from the PAD logic (PADS_DAIx_IE register) and is provided at a granularity at each DAI
pin. (Refer to the GP port chapter.) Every DAI pin can be individually controlled depending on whether the pin is
used in a system or not. The PADS register controlling the IE signal must have a reset value of 0 and hence all the
pin buffer inputs are (DAI_PBxx_O) gated to 0.
In previous SHARC products, this default value was 1 due to a weak pull-up.
NOTE:
Once the PADS module register is programmed to enable the IE signal on the used DAI pin buffers, the pin-buffer
outputs its signal on DAI_PBxx_O. The programming model needs to enable all used DAI pin buffers. For unused
DAI pin-buffers (no external system connection), keep the corresponding IE-bit at a disabled state.
33–6
DAIn_PBxx_O
PIN
DAIn_PBxx_I BUFFER
Interface
IN
to SRU
ENABLE
DAIn_PBENxx_I
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
External
OUT
DAI Pin Buffer