Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2364

Table 31-141: EMAC_MMC_TXINT Register Fields
Bit No.
(Access)
25 TXOSIZEGFIS
(RC/NW)
24 VLANFRGB
(R/NW)
23 PAUSEFRM
(R/NW)
22 EXCESSDEF
(R/NW)
21 FRCNTG
(R/NW)
20 OCTCNTG
(R/NW)
19 CARRERR
(R/NW)
18 EXCESSCOL
(R/NW)
17 LATECOL
(R/NW)
16 DEFERRED
(R/NW)
15 MULTCOLG
(R/NW)
14 SNGCOLG
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Tx Oversize Good Frame Count Interrupt Status.
The EMAC_MMC_TXINT.TXOSIZEGFIS bit is set when the txoversize_g counter
reaches half of the maximum value or the maximum value.
Tx VLAN Frames (Good) Count Half/Full.
The EMAC_MMC_TXINT.VLANFRGB bit is set when
counter reaches full or half.
Tx Pause Frames Count Half/Full.
The EMAC_MMC_TXINT.PAUSEFRM bit is set when
ter reaches full or half.
Tx Excess Deferred Count Half/Full.
The EMAC_MMC_TXINT.EXCESSDEF bit is set when
counter reaches full or half.
Tx Frame Count (Good) Count Half/Full.
The EMAC_MMC_TXINT.FRCNTG bit is set when
reaches full or half.
Tx Octet Count (Good) Count Half/Full.
The EMAC_MMC_TXINT.OCTCNTG bit is set when
reaches full or half.
Tx Carrier Error Count Half/Full.
The EMAC_MMC_TXINT.CARRERR bit is set when
reaches full or half.
Tx Excess Collision Count Half/Full.
The EMAC_MMC_TXINT.EXCESSCOL bit is set when
counter reaches full or half.
Tx Late Collision Count Half/Full.
The EMAC_MMC_TXINT.LATECOL bit is set when
reaches full or half.
Tx Deferred Count Half/Full.
The EMAC_MMC_TXINT.DEFERRED bit is set when
ter reaches full or half.
Tx Multiple collision (Good) Count Half/Full.
The EMAC_MMC_TXINT.MULTCOLG bit is set when
counter reaches full or half.
Tx Single Collision (Good) Count Half/Full.
The EMAC_MMC_TXINT.SNGCOLG bit is set when
reaches full or half.
ADSP-SC58x EMAC Register Descriptions
Description/Enumeration
EMAC_TXVLANFRM_G
EMAC_TXPAUSEFRM
EMAC_TXEXCESSDEF
EMAC_TXFRMCNT_G
EMAC_TXOCTCNT_G
EMAC_TXCARR_ERR
EMAC_TXEXCESSCOL
EMAC_TXLATECOL
EMAC_TXDEFERRED
EMAC_TXMULTCOL_G
EMAC_TXSNGCOL_G
coun-
counter
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31–273