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DAI Routing Capabilities
NOTE:
All DAI input buffers which are not routed by default are driven low and all DAI pin buffer enable signals
are driven low.
Figure 33-10: DAI0 Default Routing Pins 01-08
Figure 33-11: DAI0 Default Routing Pins 09-20
33–16
SPDIF0_RX_I
SPDIF0_TX_DAT_I
SRC3-0_DAT_IP_I
SRC3-0_TDM_OP_I
SPT0_AD0_I
SPT0_AD0_O
PBEN_O
SPT0_AD1_I
SPT0_AD1_O
PBEN_O
SPT0_ACLK_I
SPT0_ACLK_O
PBEN_O
SPT0_AFS_I
SPT0_AFS_O
PBEN_O
SPT1_AD0_I
SPT1_AD0_O
PBEN_O
SPT1_AD1_I
SPT1_AD1_O
PBEN_O
SPT1_ACLK_I
SPT1_ACLK_O
PBEN_O
SPT1_AFS_I
SPT1_AFS_O
PBEN_O
SPT1_BCLK_I
SPT1_BDLK_O
PBEN_O
SPT1_BFS_I
SPT1_BFS_O
PBEN_O
SPT1_BD0_I
SPT1_BD0_O
PBEN_O
SPT1_BD1_I
SPT1_BD1_O
PBEN_O
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SPT0_BD0_I
DAI0
SPT0_BD0_O
Pin01
PBEN_O
SPT0_BD1_I
DAI0
SPT0_BD1_O
Pin02
PBEN_O
SPT0_BCLK_I
DAI0
SPT0_BCLK_O
Pin03
PBEN_O
SPT0_BFS_I
DAI0
SPT0_BFS_O
Pin04
PBEN_O
SPT2_AD0_I
DAI0
SPT2_AD0_O
Pin09
PBEN_O
SPT2_AD1_I
DAI0
SPT2_AD1_O
Pin10
PBEN_O
SPT2_ACLK_I
SPT2_ACLK_O
PBEN_O
SPT2_AFS_I
SPT2_AFS_O
PBEN_O
SPT2_BCLK_I
DAI0
SPT2_BCLK_O
Pin13
PBEN_O
SPT2_BFS_I
DAI0
SPT2_BFS_O
Pin14
PBEN_O
SPT2_BD0_I
DAI0
SPT2_BD0_O
Pin11
PBEN_O
SPT2_BD1_I
DAI0
SPT2_BD1_O
Pin12
PBEN_O
DAI0
Pin05
DAI0
Pin06
DAI0
Pin07
DAI0
Pin08
DAI0
Pin15
DAI0
Pin16
DAI0
Pin19
DAI0
Pin20
DAI0
Pin17
DAI0
Pin18
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