Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2539

ADSP-SC58x SINC Register Descriptions
Rate Control for Group 0 Register
The register controls phase adjustments and decimation rates for primary and secondary SINC fil-
SINC_RATE0
ters assigned to group 0.
SDEC (R/W)
Secondary (Filter) Decimation Rate
SADJ (R/W)
Secondary (Filter) Adjustment
Figure 32-27: SINC_RATE0 Register Diagram
Table 32-28: SINC_RATE0 Register Fields
Bit No.
(Access)
30:25 SADJ
(R/W)
24:16 PADJ
(R/W)
32–48
15 14 13 12 11 10 9 8
0 0 0 0 1 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
Secondary (Filter) Adjustment.
The SINC_RATE0.SADJ bits provide the phase adjustment for the decimated out-
put of group 0 secondary filters. The valid adjustment is between 0 and
(SINC_RATE0.SDEC - 1), in modulator clock cycles, relative to the time the filter is
enabled in the
The secondary SINC filter calculates an output in modulator clock cycle equivalent to
( (SINC_RATE0.SDEC * n) - SINC_RATE0.SADJ ), where n is an integer > 1.
This bit field can be changed while the filter is running and takes effect after the next
decimation sample is generated. The effect of the change requires time to ripple
through the filter: a number of output sample periods is equal to the filter order.
Primary (Filter) Adjustment.
The SINC_RATE0.PADJ bits provide the phase adjustment for the decimated out-
put of group 0 primary filters. The valid adjustment is between 0 and
(SINC_RATE0.PDEC - 1), in modulator clock cycles, relative to the time the filter is
enabled in the
The primary SINC filter calculates an output in modulator clock cycle equivalent to
( (SINC_RATE0.PDEC * n) - SINC_RATE0.PADJ ), where n is an integer > 1.
This bit field can be changed while the filter is running and takes effect after the next
decimation sample is generated. The effect of the change requires time to ripple
through the filter: a number of output sample periods is equal to the filter order.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
SINC_CTL register.
SINC_CTL register.
PDEC (R/W)
Primary (Filter) Decimation Rate
PADJ (R/W)
Primary (Filter) Adjustment