SINC Event Control
• Four overload triggers, one trigger per each channel. The SINC filter module can use overload triggers to trip
the appropriate PWM block in the case of a fault. The overload trigger is always enabled, and the TRU must
assign the masters (SINC0_P0_OVLD through SINC0_P4_OVLD) to the appropriate PWM trip input slave
(PWMn_TRIP_TRIGn).
SINC Status and Error Signals
The status and error signals related to SINC operations are as follows:
•
signals:
SINC_STAT
• The amplitude and duration limit error signals for secondary SINC filters: SINC_STAT.MAX0 through
SINC_STAT.MAX3, SINC_STAT.MIN0 through SINC_STAT.MIN3, and SINC_STAT.GLIM0-
SINC_STAT.GLIM1.
• The output saturation error signals for primary SINC filters: SINC_STAT.MAX0 through
SINC_STAT.MAX3, SINC_STAT.MIN0 through SINC_STAT.MIN3, and SINC_STAT.GLIM0-
SINC_STAT.GLIM1.
• The output FIFO overflow error signals for primary SINC filters: SINC_STAT.FOVF0 and
SINC_STAT.FOVF1.
• The output count error signals for primary SINC filters: SINC_STAT.PCNT0 and
SINC_STAT.PCNT1.
• The SCB fabric-related error signals for primary SINC filters: SINC_STAT.PFAB0-
SINC_STAT.PFAB1.
•
SINC_CLK
signals:
• The phase shift signals for SINC modulator clocks: SINC_CLK.MREQ0-SINC_CLK.MREQ1.
•
SINC_HIS_STAT
• The history saved signals for secondary SINC filters: SINC_HIS_STAT.P0HISPTR through
SINC_HIS_STAT.P3HISPTR, which indicate that the data history of the filter is saved in buffer regis-
ters due to a detected overload error signal.
SINC Programming Model
The pin multiplexer enables the device input and output pins and connects the signals to the SINC module. Decide
the filter grouping in advance. The filter parameters are defined according to the control register group.
Follow these steps to configure the filters:
1. Define the primary and secondary filter parameters by setting the appropriate bits in the control register for
each filter channel group.
32–12
signals:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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