Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2570

Figure 33-15: Miscellaneous Buffer Polarity
DAI System Interrupt Controller (SIC)
The DAI module incorporates a system interrupt controller (SIC) which is connected to the SEC and GIC as seen
in the DAI System Interrupt Controller figure.
Figure 33-16: DAI System Interrupt Controller
The DAI has its own system interrupt controllers that indicate to the core when DAI audio peripheral-related events
have occurred. Since audio events generally occur infrequently relative to the SHARC core, the DAI interrupt con-
troller reduces all of its interrupts onto two interrupt signals within the core's primary interrupt systems. One inter-
rupt is mapped with DAI low priority. The second interrupt is mapped with DAI high priority. This configuration
allows programs to broadly indicate priority. In this way, the DAI SIC provides 32 independently configurable sour-
ces or channels. The output bus interrupt signals are logically OR'ed into one interrupt line and fed to the interrupt
controller logic of the core.
Three registers are used to configure the DAI interrupt controller. Each of the 32 interrupt sources can be independ-
ently configured to trigger on a rising edge, falling edge, both edges, or neither edge of an incoming signal. All DAI
interrupt control registers are memory-mapped registers and are accessed through the peripheral bus.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DAIn_MISCA0_I
SOURCE SIGNALS
DAIn_PB01_O
...
DAIn_PB20_O
SPT0_CLK_O
...
32:1
MUX
SPT5_CLK_O
DAI_INT_22
LOGIC LOW (0)
LOGIC HIGH (1)
DAIn_MISCA0_I
5-Bit Select Field
32 DAI INTERRUPT CHANNELS
DAI SIC
CLR
INTERRUPT
CONTROL
31-0
high
DAI_IRPTL_L
DAI_IRPTL_L
OR
SMMR BUS
HIGH PRIORITY
INTERRUPT
SEC
DESTINATION SIGNALS
DAIn_MISCA4_I DAIn_MISCA5_I
EX EX
OR OR
32:1 32:1
MUX MUX
BIT 30
DAIn_MISCA4_I DAIn_MISCA5_I
5-Bit Select Field 5-Bit Select Field
DAI_IMASK_PRI
DAI_IMASK_RE
DAI_IMASK_FE
low
OR
LOW PRIORITY
INTERRUPT
GIC
DAI System Interrupt Controller (SIC)
BIT 31
33–19