Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2504

2. Set the upper and lower overload limits to maximum for each channel to avoid overload trips due to the filter
startup transient.
3. Define the modulator clock frequency and startup mode.
4. Enable the SINC channels and assign them to the selected group of control registers.
Set the running overload limits after the filter settles, which is (order × decimation) modulator clock cycles after
startup. When the filters are running, the module transfers its data to data RAM on the dedicated DMA channels.
Once configured, the control registers do not need accessing, but the status and some data buffer registers typically
are read after fault events.
In general, adjusting filter parameters during operation leads to unpredictable results. However, programs can write
to the trigger and interrupt mask registers, as well as to the secondary threshold level registers during operation.
The DC gain of the converter subsystem depends on the gain of the input modulator (G
decimation rate (D). The primary filter has an output binary scalar (s) to fit data into a 16-bit range:
O S
G = 0.625 × (D ÷ 2
M
SINC Programming Concepts
Using the features and event control for the SINC to their greatest potential requires an understanding of some
SINC-related concepts:
•
Channel Configuration
•
Trigger Masking
•
Interrupt Masking
•
Modulator Clock
•
Filter Configuration
•
Primary Filter Parameters
•
Primary DMA Configuration and Data Interrupts
•
Secondary Filter Parameters
•
Overload Detection
Channel Configuration
The control bits, SINC_CTL.EN0 through SINC_CTL.EN3, configure SINC module channels. These control
bits enable or disable the selected SINC filter channel and assign the channel to control register group 0.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
)
SINC Programming Model
), filter order (O), and
M
32–13