Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2511

ADSP-SC58x SINC Register Descriptions
Clock Control Register
The register generates and enables two SINC modulator clocks. The register also controls each clock's
SINC_CLK
output, frequency, phase, and start-up behavior.
15
0
MDIV0 (R/W)
Modulator (Clock) Divider for Group 0
MREQ0 (R/W1S)
Modulator (Clock) Request for Group
0 Status
31
0
MDIV1 (R/W)
Modulator (Clock) Divider for Group 1
MREQ1 (R/W1S)
Modulator (Clock) Request for Group
1 Status
Figure 32-8: SINC_CLK Register Diagram
Table 32-9: SINC_CLK Register Fields
Bit No.
(Access)
31:26 MDIV1
(R/W)
24 MREQ1
(R/W1S)
23:18 MADJ1
(R/W)
32–20
14 13 12 11 10 9 8 7
0 0 1 0 0 0 0 0
30 29 28 27 26 25 24 23
0 0 1 0 0 0 0 0
Bit Name
Modulator (Clock) Divider for Group 1.
The SINC_CLK.MDIV1 bits provide the SCLK0_0 divider to generate the modula-
tor clock for group 1. The valid value is between 1 and 63.
Modulator (Clock) Request for Group 1 Status.
The SINC_CLK.MREQ1 bit indicates status for a phase shift request of the modula-
tor clock for group 1.
If the bits state is changed from clear (=0) to set (=1), the following modulator clock 1
period is lengthened by the number of SCLK0_0 periods specified by the
SINC_CLK.MADJ1 bits. Any writes to this bit while the bit is set are ignored. The
bit is cleared by hardware (and only by hardware) once a requested modulator clock
adjustment is complete.
Modulator (Clock) Adjustment for Group 1.
The SINC_CLK.MADJ1 bits provide the adjustment value for the modulator clock
of group 1. The valid value is between 1 and 63 when SINC_CLK.MREQ1 is set
(=1). A write to this bit field effects only an active modulator clock adjustment. See the
SINC_CLK.MREQ1 bit filed description.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
6 5 4 3 2 1 0
0 0 0 0 0 0 0
MCEN0 (R/W)
Modulator (Clock) Enable for Group 0
MADJ0 (R/W)
Modulator (Clock) Adjustment for Group 0
22 21 20 19 18 17 16
0 0 0 0 0 0 0
MCEN1 (R/W)
Modulator (Clock) Enable for Group 1
MADJ1 (R/W)
Modulator (Clock) Adjustment for Group 1
Description/Enumeration
0 Inactive
1 Active