Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2512

Table 32-9: SINC_CLK Register Fields (Continued)
Bit No.
(Access)
17:16 MCEN1
(R/W)
15:10 MDIV0
(R/W)
8 MREQ0
(R/W1S)
7:2 MADJ0
(R/W)
1:0 MCEN0
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Modulator (Clock) Enable for Group 1.
The SINC_CLK.MCEN1 bits enable/disable the modulator clock for group 1 and
control the clocks start-up behavior. Commence the clock immediately upon making it
enabled, or enable and commence upon the next rising edge of PWMSYNC (PWM
synchronizing output clock).
Modulator (Clock) Divider for Group 0.
The SINC_CLK.MDIV0 bits provide the SCLK0_0 divider to generate the modula-
tor clock for group 0. The valid value is between 1 and 63.
Modulator (Clock) Request for Group 0 Status.
The SINC_CLK.MREQ0 bit indicates status for a phase shift request of the modula-
tor clock for group 0.
If the bits state is changed from clear (=0) to set (=1), the following modulator clock 0
period is lengthened by the number of SCLK0_0 periods specified by the
SINC_CLK.MADJ0 bits. Any writes to this bit while the bit is set are ignored. The
bit is cleared by hardware (and only by hardware) once a requested modulator clock
adjustment is complete.
Modulator (Clock) Adjustment for Group 0.
The SINC_CLK.MADJ0 bits provide the adjustment value for the modulator clock
of group 0. The valid value is between 1 and 63 when SINC_CLK.MREQ1 is set
(=1). A write to this bit field effects only an active modulator clock adjustment. See the
SINC_CLK.MREQ1 bit filed description.
Modulator (Clock) Enable for Group 0.
The SINC_CLK.MCEN0 bits enable/disable the modulator clock for group 0 and
control the clocks start-up behavior. Commence the clock immediately upon making it
enabled, or enable and commence upon the next rising edge of PWMSYNC (PWM
synchronizing output clock).
ADSP-SC58x SINC Register Descriptions
Description/Enumeration
0 Disable
1 Reserved
2 Enable and Commence
3 Enable and Commence on Next Rising Edge
0 Inactive
1 Active
0 Disable
1 Reserved
2 Enable and Commence
3 Enable and Commence on Next Rising Edge
32–21