Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2592

Table 33-18: DAI1 Group E – Miscellaneous Signals (Continued)
Selection Code
11000 (0x18)
11001 (0x19)
11010 (0x1A)
11011 (0x1B)
11100 (0x1C)
11101 (0x1D)
11110 (0x1E)
11111 (0x1F)
DAI1 Group F – Pin Output Enable Source Signals
The group F pin output enable signals are listed in the following table. The group F destinations are configured
using Pin Buffer Enable Register 0
Table 33-19: DAI1 Group F – Pin Output Enable
Selection Code
000000 (0x0)
000001 (0x1)
000010 (0x2)
000011 (0x3)
000100 (0x4)
000101 (0x5)
000110 (0x6)
000111 (0x7)
001000 (0x8)
001001 (0x9)
001010 (0xA)
001011 (0xB)
001100 (0xC)
001101 (0xD)
001110 (0xE)
001111 (0xF)
010000 (0x10)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Source Signal
SPT6_AFS_O
SPT6_BFS_O
SPDIF1_TX_BLKSTART_O
PCG0_FSC_O
PCG0_CLKD_O
PCG0_FSD_O
LOW
HIGH
through Pin Buffer Enable Register 3
Source Signal
LOW
HIGH
DAI1_MISCA0_O
DAI1_MISCA1_O
DAI1_MISCA2_O
DAI1_MISCA3_O
DAI1_MISCA4_O
DAI1_MISCA5_O
SPT4_ACLK_PBEN_O
SPT4_AFS_PBEN_O
SPT4_AD0_PBEN_O
SPT4_AD1_PBEN_O
SPT4_BCLK_PBEN_O
SPT4_BFS_PBEN_O
SPT4_BD0_PBEN_O
SPT4_BD1_PBEN_O
SPT5_ACLK_PBEN_O
Description (Source Selection)
SPORT 6 Frame Sync A
SPORT 6 Frame Sync B
SPDIF 1 TX Block Start Output
Precision Frame Sync C
Precision Clock D
Precision Frame Sync D
Logic Level Low (0) as a Source
Logic Level High (1) as a Source
.
Description (Source Selection)
Logic Level Low (0)
Logic Level High (1)
DAI1 Miscellaneous Control A0 Output
DAI1 Miscellaneous Control A1 Output
DAI1 Miscellaneous Control A2 Output
DAI1 Miscellaneous Control A3 Output
DAI1 Miscellaneous Control A4 Output
DAI1 Miscellaneous Control A5 Output
SPORT 4 Clock A Output Enable
SPORT 4 Frame Sync A Output Enable
SPORT 4 Data AD0 Output Enable
SPORT 4 Data AD1 Output Enable
SPORT 4 Clock B Output Enable
SPORT 4 Frame Sync B Output Enable
SPORT 4 Data BD0 Output Enable
SPORT 4 Data BD1 Output Enable
SPORT 5 Clock A Output Enable
DAI Sources Overview
33–41