Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2502

SINC_LEVEL0.PCNT-SINC_LEVEL1.PCNT bits. Write 1 to clear the bits before the next data
transfer to generate a trigger.
• Primary filter data buffer errors:
A number of status bits indicate data buffer errors. The status bits SINC_STAT.FOVF0 and
SINC_STAT.FOVF1 indicate the filter control group when there is a SINC data buffer overflow. This
error occurs when a third sample is presented to the buffer before the first sample transfers to memory.
The status bits SINC_STAT.PFAB0 and SINC_STAT.PFAB1 indicate the filter group when an error
occurs while writing the data to memory.
• SINC status interrupt request:
There is a single SINC filter interrupt request output that can indicate secondary filter overload errors,
primary filter data saturation, or primary filter data buffer overrun. There is one interrupt mask bit for
each of these conditions per filter group. See
SINC Event Control
The SINC provides status and error bits through different registers to signal the core about its state and various error
conditions that occur during its operation. These conditions include:
• Interrupt status related to data overload, data saturation, data FIFO fault conditions
• Error status related to SINC operations
• History status (which do not generate interrupts) related to data FIFO operations
SINC Interrupt Signals
The interrupt request and trigger signals to the SINC filter module include:
• One interrupt request signal, SINC_STAT, triggered by fault events, such as detected overload limits and data
transfer errors. Manage interrupt request generation with the masking bits in the
• Bits SINC_CTL.ELIM0-SINC_CTL.ELIM1 can enable (unmask) interrupt request generation on
overload faults when the SINC_STAT.GLIM0-SINC_STAT.GLIM1 bit is set, respectively.
• Bits SINC_CTL.ESAT0-SINC_CTL.ESAT1 can mask interrupt request generation on data saturation
faults when the SINC_STAT.GSAT0-SINC_STAT.GSAT1 bit is set, respectively.
• Bits SINC_CTL.EFOVF0-SINC_CTL.EFOVF1 can mask interrupt request generation on data buffer
overruns when the SINC_STAT.FOVF0-SINC_STAT.FOVF1 bit is set, respectively.
The fault bits in the
• Two data count triggers, one trigger per each control group. The SINC filter module regularly uses the data
count triggers to generate a software interrupt request or trigger an event. First, set the SINC_CTL.EPCNT0
or SINC_CTL.EPCNT1 masking bit to enable the data count trigger. Then, the TRU must assign the data
count master (SINC0_DATA0-1) to an interrupt request input.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register must be cleared to clear the interrupt request.
SINC_STAT
Interrupt Masking for more information.
SINC Event Control
register:
SINC_CTL
32–11