SINC Architectural Concepts
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Figure 32-5: Frequency Response
Output Scaling
The output scaling and postprocessing functions embedded in the SINC filter blocks differ, depending on the func-
tion. The primary filter used for feedback signal processing includes the output bias and scaling blocks to present a
16-bit signed integer to the control code. The scaling is required at decimation rates higher than 32 to keep the
lower 16 bits of the output word.
The secondary filter supports overload detection functions. The secondary filter can detect signals crossing maxi-
mum and minimum thresholds. It has a glitch filter that only accepts faults with a minimum number of counts (c)
within a certain count window (w). The secondary filter has no output scaling, so the minimum and maximum
values in the overload registers must be calculated from the DC gain of the secondary filter. The response time to a
step input is approximately 2 x O decimation clock cycles.
32–8
FREQUENCY RESPONSE FOR 8 MHZ MODULATION
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FREQUENCY (kHz)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
D = 160
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