Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2572

Shadow Interrupt Register
The DAI interrupt controller has shadow registers to simplify debug activities since these registers do not manipulate
status control. Any read of the shadow registers (DAI_IRPTL_HS, DAI_IRPTL_LS), provides the same data as a
read of the DAI_IRPTL_H
change the interrupt acknowledge status to the core interrupt controller.
Interrupt Service
The interrupt acknowledge operates differently when multiple channels are multiplexed into one interrupt output
signal. When an interrupt from the DAI must be serviced, any of the two interrupt service routines
(INTR_DAI_IRQL, INTR_DAI_IRQH) must query the SIC to determine the source(s). Sources can be any one or
more of the DAI channels (DAI_INT31-0).
• When the
DAI_IRPTL_H
• When the
DAI_IRPTL_L
If an interrupt occurs in the same cycle as a latch register is cleared, the clear mechanism has lower priority and the
new interrupt is registered.
Signal Routing Unit Effect Latency
After the DAIy registers are configured the effect latency is 2 SCLK0 cycles minimum and 3 SCLK0 cycles maxi-
mum.
DAI Programming Model
As discussed in the previous sections, the signal routing unit is controlled by writing values that provide a plug-in
tool in CCES so that configuring the SRU is done graphically. Analog Devices offers macros that are included with
the CrossCore or VisualDSP++ tools, greatly easing code development in the SRU.
There is a macro that has been created to connect peripherals used in a DAI configuration. This code can be used in
both assembly and C code. See the INCLUDE file SRU.H. In practice the macro is provided and forms the style
SRU(source_O, destination_I) for DAI0 and SRU2(source_O, destination_I) for DAI1.
Example appears as: SRU(DAI0_PB12_O, SPT0_ACLK_I); or SRU2(DAI1_PB14_O,
SPT4_ACLK_I);
Debug Features
The following section describes the feature that can be used to help in debugging the DAI.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
and DAI_IRPTL_L registers. However, reads of the DAI shadow registers do not
register is read, the high priority latched interrupts are cleared.
register is read, the low priority latched interrupts are cleared.
Signal Routing Unit Effect Latency
33–21