Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2430

Table 31-201: EMAC_TM_CTL Register Fields (Continued)
Bit No.
(Access)
13 TSIPV4ENA
(R/W)
12 TSIPV6ENA
(R/W)
11 TSIPENA
(R/W)
10 TSVER2ENA
(R/W)
9 TSCTRLSSR
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Time Stamp IPV4 (PTP Frames) Enable.
The EMAC_TM_CTL.TSIPV4ENA bit, when set, directs the EMAC receiver to
process the PTP packets encapsulated in UDP over IPv4 packets. When this bit is
clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by
default.
Time Stamp IPV6 (PTP Frames) Enable.
The EMAC_TM_CTL.TSIPV6ENA bit, when set, directs the EMAC receiver to
process PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear,
the MAC ignores the PTP transported over UDP-IPv6 packets.
Time Stamp IP Enable.
The EMAC_TM_CTL.TSIPENA bit, when set, directs the EMAC receiver to process
the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear,
the MAC ignores PTP over Ethernet packets.
Time Stamp VER2 (Snooping) Enable.
The EMAC_TM_CTL.TSVER2ENA bit, when set, processes the PTP packets using
the 1588 version 2 format (enables PTP packet snooping for VER2) else processed us-
ing the version 1 format.
Time Stamp Control Nanosecond Rollover.
The EMAC_TM_CTL.TSCTRLSSR bit, when set, rolls over the
register after 0x3B9A_C9FF value (10
ter. When reset, the roll over value of
nanosecond increment has to be programmed correctly depending on the PTP refer-
ence clock frequency and this bit value.
ADSP-SC58x EMAC Register Descriptions
Description/Enumeration
0 Disable Time Stamp for PTP Over IPv4 Frames
1 Enable Time Stamp for PTP Over IPv4 Frames
0 Disable Time Stamp for PTP Over IPv6 frames
1 Enable Time Stamp for PTP Over IPv6 Frames
0 Disable PTP Over Ethernet Frames
1 Enable PTP Over Ethernet Frames
0 Disable packet snooping for V2 frames
1 Enable packet snooping for V2 frames
9
-1) and increments the
EMAC_TM_NSEC
0 Roll Over Nanosecond After 0x7FFFFFFF
1 Roll Over Nanosecond After 0x3B9AC9FF
EMAC_TM_NSEC
EMAC_TM_SEC regis-
register is 0x7FFF_FFFF. The
31–339