Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2590

Table 33-17: DAI1 Group D – Pin Signal Assignments (Continued)
Selection Code
0111001 (0x39)
0111010 (0x3A)
0111011 (0x3B)
0111100 (0x3C)
0111101 (0x3D)
0111110 (0x3E)
0111111 (0x3F)
1000000 (0x40)
1000001 (0x41)
1000010 (0x42)
1000011 (0x43)
1000100 (0x44)
1000101 (0x45)
1000110 (0x46)
1000111 (0x47)
1001000 (0x48)
1001001 (0x49)
1001010 (0x4A)
1001011 (0x4B)
1001100 (0x4C)
1001101 (0x4D)
1001110 (0x4E)
1001111 (0x4F)
1010000 (0x50)
1010001 (0x51)
1010010 (0x52)
1010011 (0x53)
1010100 (0x54)
1010101 (0x55)
1010110 – 1111101
1111110 (0x7E)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Source Signal
PCG0_CLKD_O
PCG0_FSC_O
PCG0_FSD_O
Reserved
SRC4_DAT_OP_O
SRC5_DAT_OP_O
SRC6_DAT_OP_O
SRC7_DAT_OP_O
SPDIF1_RX_DAT_O
SPDIF1_FS_O
SPDIF1_RXCLK_O
SPDIF1_RX_TDMCLK_O
SPDIF1_TX_O
SPT4_ATDV_O
SPT4_BTDV_O
SPT5_ATDV_O
SPT5_BTDV_O
SPT6_ATDV_O
SPT6_BTDV_O
SPT7_ATDV_O
SPT7_BTDV_O
Reserved
Reserved
PCG0_CRS_CLKA_O
PCG0_CRS_CLKB_O
PCG0_CRS_FSA_O
PCG0_CRS_FSB_O
DAI1_CRS_PB03_O
DAI1_CRS_PB04_O
Reserved
LOW
DAI Sources Overview
Description (Source Selection)
Precision Clock D
Precision Frame Sync C
Precision Frame Sync D
SRC4 Data Output
SRC5 Data Output
SRC6 Data Output
SRC7 Data Output
SPDIF 1 RX Data Output
SPDIF 1 RX Frame Sync Output
SPDIF 1 RX Clock Output
SPDIF 1 RX TDM Clock Output
SPDIF 1 TX Biphase Encoded Data
Output
SPORT4 Transmit A Data Valid Output
SPORT4 Transmit B Data Valid Output
SPORT5 Transmit A Data Valid Output
SPORT5 Transmit B Data Valid Output
SPORT6 Transmit A Data Valid Output
SPORT6 Transmit B Data Valid Output
SPORT7 Transmit A Data Valid Output
SPORT7 Transmit B Data Valid Output
Precision Clock A (DAI0)
Precision Clock B (DAI0)
Precision Frame Sync A (DAI0)
Precision Frame Sync B (DAI0)
Pin Buffer 3 (DAI0)
Pin Buffer 4 (DAI0)
Logic Level Low (0)
33–39