Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2564

Miscellaneous Buffers and Functions
The SRU group E provides miscellaneous buffers used for group interconnect.
DAI group E connections are slightly different from the others in that the inputs and outputs being routed vary
considerably in function. This group routes control signals and provides a means of connecting signals between
groups.
In the DAI MISCAx SRU Signal Connections table, the DAIn_MISCAx_I signals appear as inputs in group E
(also connected to the DAI interrupt logic), but do not directly feed any peripheral. Rather, the MISCAx_O signals
reappear as outputs in group F.
Table 33-3: DAI MISCAx SRU Signal Connections
MISCA Source
DAIn_MISCA5-0_O
Additional connections among groups provide a great amount of utility. Since the output groups F (DAI) dictate pin
direction, these few signal paths enable a number of possible uses and connections for the DAI pins. Other examples
include:
• A pin input can be patched to another pin's enable, allowing an off-chip signal to gate an output from the
processor.
• Any of the DAI pins can be used as interrupt sources or general-purpose I/O (GPIO) signals.
In summary, the SRU enables many possible functional changes, both within the processor as well as externally.
Used creatively, it allows system designers to radically change functionality at run time, and to potentially reuse cir-
cuit boards across many products.
DAI Routing Capabilities
This section describes the routing options to aid in designing a system using the DAI units. The
nections section provides information on connecting signals across DAI0 and DAI1. The
section provides diagrams that show how that DAIs connect at default. The DAI Group tables provide the source
signals and selections codes. Finally, the
figuring destinations.
The DAI Routing Capabilities tables provide an overview of the different routing capabilities for the DAI unit. For
information on an individual peripherals routing, see the "SRU Programming" section of the specific peripheral
chapter.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DAI Connection
Group E
Group F
ADSP-SC58x DAI Register Descriptions
Functional Description
MISCA Destination
DAIn_MISCA5-0_I
Cross Mode Con-
DAI Default Routing
provides information about con-
33–13