Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2334

Layer 3 Address3 Register
The
EMAC_L3_ADDR3
Source Address field.
Figure 31-98: EMAC_L3_ADDR3 Register Diagram
Table 31-130: EMAC_L3_ADDR3 Register Fields
Bit No.
(Access)
31:0 L3A3
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register tells For IPv4 frames, the Layer 3 Address 3 Register 0 contains the 32-bit IP
15 14
0
L3A3[15:0] (R/W)
Layer 3 Address 3 Field
31 30
0
L3A3[31:16] (R/W)
Layer 3 Address 3 Field
Bit Name
Layer 3 Address 3 Field.
The EMAC_L3_ADDR3.L3A3 bits, When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are
set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the
value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames.
When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Lay-
er 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of
the IP Destination Address field in the IPv6 frames. When Bit 0 (L3PEN0) is reset
and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0),
this field contains the value to be matched with the IP Source Address field in the IPv4
frames.
13 12 11 10 9 8 7 6
0 0 0 0 0 0 0 0 0
29 28 27 26 25 24 23 22
0 0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x EMAC Register Descriptions
5 4 3 2 1 0
0 0 0 0 0 0
21 20 19 18 17 16
0 0 0 0 0 0
31–243