Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2574

Table 33-8: DAI0 Group A – Clock Routing (Continued)
Selection Code
01001 (0x9)
01010 (0xA)
01011 (0xB)
01100 (0xC)
01101 (0xD)
01110 (0xE)
01111 (0xF)
10000 (0x10)
10001 (0x11)
10010 (0x12)
10011 (0x13)
10100 (0x14)
10101 (0x15)
10110 (0x16)
10111 (0x17)
11000 (0x18)
11001 (0x19)
11010 (0x1A)
11011 (0x1B)
11100 (0x1C)
11101 (0x1D)
11110 (0x1E)
11111 (0x1F)
DAI0 Group B – Serial Data Source Signals
The group B data sources are listed in the following table. The group B data destinations are configured using
Data Routing Control Register 0
Table 33-9: DAI0 Group B – Serial Data Signals
Selection Code
000000 (0x0)
000001 (0x1)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Source Signal
DAI0_PB10_O
DAI0_PB11_O
DAI0_PB12_O
DAI0_PB13_O
DAI0_PB14_O
DAI0_PB15_O
DAI0_PB16_O
DAI0_PB17_O
DAI0_PB18_O
DAI0_PB19_O
DAI0_PB20_O
SPT0_ACLK_O
SPT0_BCLK_O
SPT1_ACLK_O
SPT1_BCLK_O
SPT2_ACLK_O
SPT2_BCLK_O
SPDIF0_RX_CLK_O
SPDIF0_RX_TDMCLK_O
PCG0_CLKA_O
PCG0_CLKB_O
LOW
HIGH
through Serial Data Routing Control Register 6
Source Signal
DAI0_PB01_O
DAI0_PB02_O
DAI Sources Overview
Description (Source Selection)
Pin Buffer 10
Pin Buffer 11
Pin Buffer 12
Pin Buffer 13
Pin Buffer 14
Pin Buffer 15
Pin Buffer 16
Pin Buffer 17
Pin Buffer 18
Pin Buffer 19
Pin Buffer 20
SPORT 0 Clock A
SPORT 0 Clock B
SPORT 1 Clock A
SPORT 1 Clock B
SPORT 2 Clock A
SPORT 2 Clock B
SPDIF 0 Receive Clock Output
SPDIF 0 Receive TDM Clock Output
Precision Clock A Output
Precision Clock B Output
Logic Level Low (0)
Logic Level High (1)
.
Description (Source Selection)
Pin Buffer 1
Pin Buffer 2
Serial
33–23