Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2341

ADSP-SC58x EMAC Register Descriptions
Table 31-134: EMAC_MACCFG Register Fields (Continued)
Bit No.
(Access)
16 DCRS
(R/W)
15 PS
(R/NW)
14 FES
(R/W)
13 DO
(R/W)
12 LM
(R/W)
11 DM
(R/W)
10 IPC
(R/W)
31–250
Bit Name
Disable Carrier Sense.
The EMAC_MACCFG.DCRS bit, when set, makes the MAC transmitter ignore the
CRS signal during frame transmission in Half-Duplex mode. This request results in no
errors generated due to Loss of Carrier or No Carrier during such transmission. When
this bit is low, the MAC transmitter generates such errors due to Carrier Sense and will
even abort the transmissions.
Port Select.
The EMAC_MACCFG.PS bit selects between GMII and MII as: 0=GMII (1000
Mbps) and 1=MII (10/100 Mbps). This bit is read-only with the appropriate value in
the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, and
R_W in the default 10/100/1000 Mbps configuration.
Speed of Operation.
The EMAC_MACCFG.FES bit indicates the Ethernet speed as 10 Mbps (bit =0) or
100 Mbps (bit =1).
Disable Receive Own.
The EMAC_MACCFG.DO bit, when set, disables MAC reception of frames when
MAC is transmitting in Half-Duplex mode. When this bit is reset, the MAC receives
all packets that are given by the PHY while transmitting. This bit is not applicable if
the MAC is operating in Full-Duplex mode.
Loopback Mode.
The EMAC_MACCFG.LM bit, when set, directs the MAC to operate in internal loop
back mode. (The media independent interface pins are not driven or sampled.)
Duplex Mode.
The EMAC_MACCFG.DM bit, when set, directs the MAC to operate in a Full-Duplex
mode where it can transmit and receive simultaneously.
IP Checksum.
The EMAC_MACCFG.IPC bit, when set, directs the MAC to calculate the 16-bit
one's complement of the one's complement sum of all received Ethernet frame pay-
loads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25-26 or
29-30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame
and gives the status in the receive status word. The EMAC_MACCFG.IPC bit, when
set, enables IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP
headers. When this bit is reset, the Checksum Offload Engine function in the receiver
is disabled and the corresponding PCE and IP HCE status bits are always cleared.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
5 56 bit times
6 48 bit times
7 40 bit times