Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2526

Sharc+ processor
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(Amplitude) Limits for Secondary Filter 1 Register
The
register controls amplitude limits for a secondary filter of SINC pair 1.
SINC_LIMIT1
Figure 32-14: SINC_LIMIT1 Register Diagram
Table 32-15: SINC_LIMIT1 Register Fields
Bit No.
(Access)
31:16
LMAX
(R/W)
15:0
LMIN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
0
0
0
LMIN (R/W)
Limit Minimum for Secondary Filter 1
31
30
29
0
0
0
LMAX (R/W)
Limit Maximum for Secondary Filter 1
Bit Name
Limit Maximum for Secondary Filter 1.
The SINC_LIMIT1.LMAX bits specify the output signal conditions for the secon-
dary SINC filter 1. In conjunction with bits LCNT and LWIN in register
SINC_LEVEL1
ed maximum limit warning bit in register SINC_STAT.
Limit Minimum for Secondary Filter 1.
The SINC_LIMIT1.LMIN bits specify the output signal conditions for the secon-
dary SINC filter 1. In conjunction with bits LCNT and LWIN in register
SINC_LEVEL1
ed minimum limit warning bit in register SINC_STAT.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
or SINC_LEVEL0, this bit field specifies conditions for an associat-
or SINC_LEVEL0, this bit field specifies conditions for an associat-
ADSP-SC58x SINC Register Descriptions
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
32–35

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