Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2571

DAI System Interrupt Controller (SIC)
Interrupt Sources
The DAI's five peripheral sources are multiplexed into 32 interrupt sources and are labeled DAI_INT31-0 (DAI
Interrupt Sources table).
NOTE: There are two naming conventions. The DAI interrupt controller register bits are labeled DAI_31-0_INT.
Their corresponding SRU routing signals are labeled DAI_INT_31-0_I.
Table 33-6: DAI Interrupt Sources
Interrupt Source
DAI_INT2–0, DAI_INT4
DAI_INT2–0, DAI_INT4
DAI_INT21–18
DAI_INT31–22
Interrupt Latch Priority Option
The
DAI_IMSK_PRI
ler has a pair of interrupt latch registers,
DAI_IMSK_PRI register also determines the interrupt latch mapping for a particular DAI interrupt. When a DAI
interrupt is configured as low priority
DAI_INTR_IRQL signal and when an interrupt occurs, the corresponding bit of the
set. When a DAI interrupt is configured as high priority
DAI_INTR_IRQH signal and the interrupt is latched to the
rupt (INTR_DAI_IRQL) and high priority DAI interrupt (INTR_DAI_IRQH) are connected to the SEC and
GIC.
Interrupt Mask for Waveforms
The and
DAI_IMSK_RE
of a signal mapped to the channel. It can be configured for rising edges, falling edges, both rising and falling edges,
or neither rising nor falling edges by masking them separately. Signals from the SRU can be used to generate inter-
rupts. For example, when the DAI_IMSK_FE.MISCINT9 bit is set to one, any falling edge signals from the ex-
ternal channel generate an interrupt and the interrupt latch is set.
Interrupt Mask for Events
The system interrupt controller needs information about a peripheral's interrupt sources that correspond to event
signals (see the DAI Interrupt Sources table). As a result, the rising edge is used as an interrupt source only. For DAI
peripherals marked as events, programs may unmask an interrupt source on the rising edge only.
33–20
Description
S/PDIF RX, 4 channels
S/PDIF RX, 4 channels
ASRC, 4 channels
Miscellaneous, S/PDIF TX, 9 channels
register specifies the priority for the DAI interrupt channels. DAI system interrupt control-
DAI_IRPTL_H
(DAI_IMSK_PRI
registers allow programs to mask or unmask interrupts for specific edges
DAI_IMSK_FE
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Signal Response
Event
Waveform
and DAI_IRPTL_L. The configuration of the
bit cleared, default setting), interrupts are mapped to the
(DAI_IMSK_PRI bit set), interrupts are mapped to the
register. The low priority DAI inter-
DAI_IRPTL_H
DAI_IRPTL_L register is