Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2510

Sharc+ processor
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Bias for Group 1 Register
The
register controls an output bias added to primary SINC filters of group 1.
SINC_BIAS1
Figure 32-7: SINC_BIAS1 Register Diagram
Table 32-8: SINC_BIAS1 Register Fields
Bit No.
(Access)
31:0
BIAS
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
0
BIAS[15:0] (R/W)
Bias for Group1 Primary Filters
31
30
0
BIAS[31:16] (R/W)
Bias for Group1 Primary Filters
Bit Name
Bias for Group1 Primary Filters.
The SINC_BIAS1.BIAS bits specify a bias for the primary SINC filters output.
The bias is added to the output prior to saturation and DMA memory transfer. The
valid value is represented in two's complement format; thus, must be programmed to
be equal to -(d ^ o) / 2, where where d = SINC_RATE1.PDEC and o =
SINC_LEVEL1.PORD.
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x SINC Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
0
32–19

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