Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2544

Table 32-30: SINC_STAT Register Fields
Bit No.
(Access)
31 GLIM1
(R/NW)
30 GSAT1
(R/NW)
29 PCNT1
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Group 1 Limit Status.
The SINC_STAT.GLIM1 indicates status for an amplitude and duration limit of
secondary SINC filters assigned to group 1. This bit is set (=1) if any limit specified by
registers SINC_LIMIT3, SINC_LIMIT2, SINC_LIMIT1, or SINC_LIMIT0,
within the duration count and window specified by bits SINC_LEVEL0.LCNT and
SINC_LEVEL0.LWIN are exceeded.
To identify the offending secondary SINC filter, examine the filters status bits
SINC_STAT.MAX3, SINC_STAT.MAX2, SINC_STAT.MAX1,
SINC_STAT.MAX0, SINC_STAT.MIN3, SINC_STAT.MIN2,
SINC_STAT.MIN1 and SINC_STAT.MAX0 according to the group 1 assignments
in the
SINC_CTL
Group 1 Saturation Status.
The SINC_STAT.GSAT1 indicates status for the output saturation bit of primary
SINC filters assigned to group 1. The bit is set (=1) if any filter of group 1 has its satu-
ration status bit set (=1).
To identify the offending SINC primary filter, examine bits SINC_STAT.PSAT3,
SINC_STAT.PSAT2, SINC_STAT.PSAT1, and SINC_STAT.PSAT0 accord-
ing to the group 1 assignments specified by the SINC_CTL.EN3, SINC_CTL.EN2,
SINC_CTL.EN1, and SINC_CTL.EN0 bits.
Primary (Filter) Count for Group 1 Status.
The SINC_STAT.PCNT1 indicates status for the output count of primary SINC fil-
ters assigned to group 1. The bit is set (=1) each time the modulo number of outputs
(specified by the SINC_LEVEL1.PCNT bits) has been transferred for each primary
SINC filter assigned to group 1. Each count in SINC_LEVEL1.PCNT corresponds
to one complete set or vector of samples from all SINC filter pairs assigned to group 1.
For example, if group 1 is assigned three SINC filters pairs 0, 1, and 3, and
SINC_LEVEL1.PCNT is set to 5, then this status bit is set after the transfer of every
5th complete sample vector, comprising 3 x 5= 15 data samples. This bit asserts when
the memory transfer on the system SCB fabric is complete, and a valid SCB write data
response is received by the SINC filter unit.
If this status bit and bit SINC_CTL.EPCNT1 are set (=1), the SINC_DATA1 trigger
is asserted. Write 1 to clear.
Description/Enumeration
register.
0 Not Exceeded
1 Exceeded
0 Not Set
1 Set
0 Not Reached
1 Reached
ADSP-SC58x SINC Register Descriptions
32–53