Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2605

ADSP-SC58x DAI Register Descriptions
Clock Routing Control Register 1
The register provides clock routing connections for the asynchronous sample rate converters (ASRC).
DAI_CLK1
IN3[0] (R/W)
Input Clock 3
IN2 (R/W)
Input Clock 2
IN5 (R/W)
Input Clock 5
IN4 (R/W)
Input Clock 4
Figure 33-18: DAI_CLK1 Register Diagram
Table 33-29: DAI_CLK1 Register Fields
Bit No.
(Access)
29:25 IN5
(R/W)
24:20 IN4
(R/W)
19:15 IN3
(R/W)
14:10 IN2
(R/W)
9:5 IN1
(R/W)
33–54
15 14 13 12 11 10
0 1 1 1 1
31 30 29 28 27 26
0 0 1 1 1
Bit Name
Input Clock 5.
DAI_CLK1.IN5 holds the Source signal assignment that will be routed to the
DAI_CLK1.IN5 Destination. Refer to the Group A Signals table for Source and
Destination mappings
Input Clock 4.
DAI_CLK1.IN4 holds the Source signal assignment that will be routed to the
DAI_CLK1.IN4 Destination. Refer to the Group A Signals table for Source and
Destination mappings
Input Clock 3.
DAI_CLK1.IN3 holds the Source signal assignment that will be routed to the
DAI_CLK1.IN3 Destination. Refer to the Group A Signals table for Source and
Destination mappings
Input Clock 2.
DAI_CLK1.IN2 holds the Source signal assignment that will be routed to the
DAI_CLK1.IN2 Destination. Refer to the Group A Signals table for Source and
Destination mappings
Input Clock 1.
DAI_CLK1.IN1 holds the Source signal assignment that will be routed to the
DAI_CLK1.IN1 Destination. Refer to the Group A Signals table for Source and
Destination mappings.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9 8 7 6 5 4 3
0 1 1 1 1 0 1 1
25 24 23 22 21 20 19 18
1 0 1 1 1 1 0 1
Description/Enumeration
2 1 0
1 1 0
IN0 (R/W)
Input Clock 0
IN1 (R/W)
Input Clock 1
17 16
1 1 1
IN3[4:1] (R/W)
Input Clock 3