Analog Devices ADSP-SC58 Series Hardware Reference Manual page 2421

ADSP-SC58x EMAC Register Descriptions
SMI Address Register
The
EMAC_SMI_ADDR
PA (R/W)
Physical Layer Address
SMIR (R/W)
SMI Register Address
CR (R/W)
Clock Range
Figure 31-164: EMAC_SMI_ADDR Register Diagram
Table 31-196: EMAC_SMI_ADDR Register Fields
Bit No.
(Access)
15:11 PA
(R/W)
10:6 SMIR
(R/W)
5:2 CR
(R/W)
31–330
register contains the station management interface address and feature settings.
15 14 13 12 11 10
0 0 0 0 0 0
31 30 29 28 27 26
0 0 0 0 0 0
Bit Name
Physical Layer Address.
The EMAC_SMI_ADDR.PA bits select the PHY. This field tells which of the 32 pos-
sible PHY devices are being accessed.
SMI Register Address.
The EMAC_SMI_ADDR.SMIR bits select the desired Station Management Interface
register in the selected PHY device.
Clock Range.
The EMAC_SMI_ADDR.CR bits select the Clock Range, determining the frequency
of the MDC clock as per the SCLK0_0 frequency. The suggested range of SCLK0_0
frequency applicable for each value below (when Bit[5] =0) ensures that the MDC
clock is approximately between the frequency range 1.0 MHz - 2.5 MHz. When the
MSB of this field is set, you can achieve MDC clock of frequency higher than the
IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of low-
er value. For example, when SCLK0_0=100 MHz and you program these bits to
b#1010, the resulting MDC clock is 12.5 MHz, which is outside the limit of IEEE
802.3 specified range. Use the values shown only if the interface chips support faster
MDC clocks.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
Description/Enumeration
0 MDC Clock= SCLK0_0/42 (for
SCLK0_0=60-100MHz)
1 MDC Clock= SCLK0_0/62 (for SCLK0_0=100-125
MHz)
2 MDC Clock= SCLK0_0/16 (for SCLK0_0=20-35
MHz)
1 0
0 0
SMIB (R/W1S)
SMI Busy
SMIW (R/W)
SMI Write
17 16
0 0