Timing Requirements For Buswidth - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
XTAL1
CLKOUT
ALE
BUSWIDTH
Bus
The BUSWIDTH signal can be used in numerous applications. For example, a system could store
code in a 16-bit memory device and data in an 8-bit memory device. The BUSWIDTH signal
could be tied to the chip-select input of the 8-bit memory device (shown in Figure 14-13 on page
14-26). When BUSWIDTH is low, it enables 8-bit bus mode and selects the 8-bit memory device.
When BUSWIDTH is high, it enables 16-bit bus mode and deselects the 8-bit memory device.

14.4.1 Timing Requirements for BUSWIDTH

When using BUSWIDTH to dynamically change between 8-bit and 16-bit bus widths, setup and
hold timings must be met for proper operation (see Figure 14-5). Because a decoded, valid ad-
dress is used to generate the BUSWIDTH signal, the setup time is specified relative to the address
being valid. This specification, T
dress and generate a valid BUSWIDTH signal.
BUSWIDTH must be held valid until the minimum hold specification, T
ically this hold time is 0 ns minimum after CLKOUT goes low. In all cases, refer to the data sheet
for current specifications for T
Earlier HMOS devices used a BUSWIDTH setup timing that was referenced to
the falling edge of ALE (T
CMOS devices, which use an internal two-phase clock; it is included for
comparison only.
14-12
T
LLGV
Valid
T
AVGV
Address
Figure 14-5. BUSWIDTH Timing Diagram
, indicates how much time one has to decode the valid ad-
AVGV
and T .
AVGV CLGX
NOTE
). This specification is not meaningful for
LLGV
T (MIN)
CLGX
Data
A0164-02
, has been met. Typ-
CLGX