Intel 8XC196NT User Manual page 427

8XC196NT USER'S MANUAL
Mnemonic
ELD EXTENDED LOAD WORD. Loads the value
of the source word operand into the
destination operand.
This instruction allows you to move data from
anywhere in the 16-Mbyte address space into
the lower register file.
ext. indirect: (DEST)
ext indexed: (DEST)
Z
—
ELDB EXTENDED LOAD BYTE. Loads the value of
the source byte operand into the destination
operand.
This instruction allows you to move data from
anywhere in the 16-Mbyte address space into
the lower register file.
ext. indirect: (DEST)
ext indexed: (DEST)
Z
—
EPTS ENABLE PERIPHERAL TRANSACTION
SERVER (PTS). Enables the peripheral
transaction server (PTS).
PTS Enable (PSW.2)
Z
—
A-18
Table A-6. Instruction Set (Continued)
Operation
←
(SRC)
←
(SRC) + 24-bit disp
PSW Flag Settings
N C V VT ST
— — — — —
←
(SRC)
←
(SRC) + 24-bit disp
PSW Flag Settings
N C V VT ST
— — — — —
←
1
PSW Flag Settings
N C V VT ST
— — — — —
Instruction Format
DEST, SRC
ELD wreg, [treg]
ext. indirect: (11101000) (treg) (wreg)
ext. indexed: (11101001) (treg) (disp-low)
(disp-high) (disp-ext) (wreg)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
DEST, SRC
ELDB breg, [treg]
ext. indirect: (11101010) (treg) (breg)
ext. indexed: (11101011) (treg) (disp-low)
(disp-high) (disp-ext) (breg)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
EPTS
(11101101)