Intel 8XC196NT User Manual page 302

Figure 12-7 shows the reset-sequence timing. Depending upon when RESET# is brought high,
the CLKOUT signal may become out of phase with the PH1 internal clock. When this occurs, the
clock generator immediately resynchronizes CLKOUT as shown in Case 2.
Internal
Reset
RESET#
Pin
Case 1
CLKOUT
Case 2
CLKOUT
Phases Resynchronized
ALE
RD#
AD7:0
18H
AD15:8
20H
A19:16
0FH Strongly Driven
†
Defaults to an 8-bit bus until the CCBs are loaded. AD15:8 strongly drive address during the CCB fetches.
For 16-bit systems, write 20H to the high byte of CCB0, CCB1, and CCB2 (FF2019H, FF201BH, and FF201DH)
in order to prevent bus contention.
The following events will reset the device (see Figure 12-8):
•
an external device pulls the RESET# pin low
•
the CPU issues the reset (RST) instruction
•
the CPU issues an idle/powerdown (IDLPD) instruction with an illegal key operand
•
the watchdog timer (WDT) overflows
•
the oscillator fail detect (OFD) circuitry is enabled and an oscillator failure occurs
The following paragraphs describe each of these reset methods in more detail.
9 T 9 T
7 T
OSC OSC
OSC
7 T 7 T
9 T
OSC OSC
OSC
CCB0 1AH CCB1
†
Strong 20H † Strong
Bus parameters defined by CCB0 (ready
control, bus width, and bus-timing
modes) take effect here.
Figure 12-7. Reset Timing Sequence
MINIMUM HARDWARE CONSIDERATIONS
= ADV# Selected
9 T
10 T
OSC
OSC
7 T
13 T
OSC
OSC
1CH CCB2
†
20H Strong
8 T
OSC
11 T
OSC
80H
20H
A0254-02
12-9