Intel 8XC196NT User Manual page 344

Figure 14-12 shows an 8-bit system with both flash and RAM. The flash is the lower half of mem-
ory, and the RAM is the upper half. This system configuration uses the most-significant address
bit (A19) as the chip-select signal and ALE as the address-latch signal. The lower address lines,
AD7:0, are latched because these lines are carry both address and data information. The upper
address lines, AD15:8, are latched only when operating in bus timing modes 1 and 2 because in
these modes, the address lines are not driven throughout the entire bus cycle. (See "Design Con-
siderations" on page 14-39).
A19
A17:16
AD15:8
8XC196
ALE
AD7:0
RD#
WR#
Applies to bus timing modes 1 and 2 only.
A15:8
74AC
373
LE
LE
74AC A7:0
373
Figure 14-12. 8-bit System with Flash and RAM
INTERFACING WITH EXTERNAL MEMORY
CS#
A17:16
A15:8
256K×8
Flash
(28F020)
D7:0
A7:0
OE#
CS#
A16
A15:8
128K×8
RAM
D7:0
A7:0
OE# WE#
A0285-02
14-25