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14.4.3
8-bit Bus Timings ..................................................................................................14-15
14.5
WAIT STATES (READY CONTROL)......................................................................... 14-17
14.6
BUS-HOLD PROTOCOL ........................................................................................... 14-19
14.6.1
Enabling the Bus-hold Protocol .............................................................................14-21
14.6.2
Disabling the Bus-hold Protocol ............................................................................14-22
14.6.3
Hold Latency .........................................................................................................14-22
14.6.4
Regaining Bus Control ..........................................................................................14-22
14.7
BUS-CONTROL MODES........................................................................................... 14-23
14.7.1
Standard Bus-control Mode ..................................................................................14-23
14.7.2
Write Strobe Mode ................................................................................................14-27
14.7.3
Address Valid Strobe Mode ..................................................................................14-29
14.7.4
Address Valid with Write Strobe Mode ..................................................................14-33
14.8
BUS TIMING MODES................................................................................................ 14-34
14.8.1
Mode 3, Standard Mode .......................................................................................14-36
14.8.2
Mode 0, Standard Timing with One Automatic Wait State ....................................14-36
14.8.3
Mode 1, Long Read/Write Mode ...........................................................................14-36
14.8.4
Mode 2, Long Read/Write with Early Address ......................................................14-37
14.8.5
Design Considerations ..........................................................................................14-39
14.9
SYSTEM BUS AC TIMING SPECIFICATIONS ......................................................... 14-39
CHAPTER 15
15.1
PROGRAMMING METHODS ...................................................................................... 15-1
15.2
OTPROM MEMORY MAP ........................................................................................... 15-2
15.3
SECURITY FEATURES............................................................................................... 15-3
15.3.1
Controlling Access to Internal Memory ...................................................................15-3
15.3.1.1
Controlling Access to the OTPROM During Normal Operation ..........................15-4
15.3.1.2
Controlling Access to the OTPROM During Programming Modes .....................15-4
15.3.2
Controlling Fetches from External Memory .............................................................15-6
15.3.3
Enabling the Oscillator Failure Detection Circuitry ..................................................15-7
15.4
PROGRAMMING PULSE WIDTH ............................................................................... 15-8
15.5
MODIFIED QUICK-PULSE ALGORITHM.................................................................... 15-9
15.6
PROGRAMMING MODE PINS.................................................................................. 15-11
15.7
ENTERING PROGRAMMING MODES ..................................................................... 15-13
15.7.1
Selecting the Programming Mode .........................................................................15-13
15.7.2
Power-up and Power-down Sequences ................................................................15-14
15.7.2.1
Power-up Sequence .........................................................................................15-14
15.7.2.2
Power-down Sequence ....................................................................................15-14
15.8
SLAVE PROGRAMMING MODE............................................................................... 15-15
15.8.1
Reading the Signature Word and Programming Voltages ....................................15-15
15.8.2
Slave Programming Circuit and Memory Map ......................................................15-16
15.8.3
Operating Environment .........................................................................................15-17
15.8.4
Slave Programming Routines ...............................................................................15-19
CONTENTS
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