Table of Contents
Advertisement
2.3.1
CPU Control
The CPU is controlled by the microcode engine, which instructs the RALU to perform operations
using bytes, words, or double words from either the 256-byte lower register file or through a win-
dow that directly accesses the upper register file. (See Chapter 4, "Memory Partitions," for more
information about the register file and windowing.) CPU instructions move from the 4-byte queue
in the memory controller into the RALU's instruction register. The microcode engine decodes the
instructions and then generates the sequence of events that cause desired functions to occur.
2.3.2
Register File
The register file is divided into an upper and a lower file. In the lower register file, the lowest 24
bytes are allocated to the CPU's special-function registers (SFRs) and the stack pointer, while the
remainder is available as general-purpose register RAM. The upper register file contains only
general-purpose register RAM. The register RAM can be accessed as bytes, words, or double-
words.
The RALU accesses the upper and lower register files differently. The lower register file is always
directly accessible with direct addressing (see "Addressing Modes" on page 3-6). The upper reg-
ister file is accessible with direct addressing only when windowing is enabled. Windowing is a
technique that maps blocks of the upper register file into a window in the lower register file. See
Chapter 4, "Memory Partitions," for more information about the register file and windowing.
2.3.3
Register Arithmetic-logic Unit (RALU)
The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master pro-
gram counter (PC), the processor status word (PSW), and several registers. The registers in the
RALU are the instruction register, a constants register, a bit-select register, a loop counter, and
three temporary registers (the upper-word, lower-word, and second-operand registers).
The PSW contains one bit (PSW.1) that globally enables or disables servicing of all maskable in-
terrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six
Boolean flags that reflect the state of your program. Appendix A, "Instruction Set Reference,"
provides a detailed description of the PSW.
The device has a 24-bit program counter (PC), which provides a linear, nonsegmented 16-Mbyte
memory space. Only 20 of the address lines are implemented with external pins, so you can phys-
ically address only 1 Mbyte. (For compatibility with earlier devices, the PC can be configured as
16 bits wide.) The PC contains the address of the next instruction and has a built-in incrementer
that automatically loads the next sequential address. However, if a jump, interrupt, call, or return
changes the address sequence, the ALU loads the appropriate address into the PC.
ARCHITECTURAL OVERVIEW
2-3
Advertisement
Table of Contents
