Intel 8XC196NT User Manual page 328

CCR1 (Continued)
The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing
mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. Another bit
controls whether CCR2 is loaded.
7
MSEL1 MSEL0
Bit Bit
Number Mnemonic
1 IRC2
0 LDCCB2
Figure 14-2. Chip Configuration 1 (CCR1) Register (Continued)
INTERFACING WITH EXTERNAL MEMORY
0 1
Ready Control
This bit, along with IRC0 (CCR0.4) and IRC1 (CCR0.5), limits the
number of wait states that can be inserted while the READY pin is held
low. Wait states are inserted into the bus cycle either until the READY
pin is pulled high or until this internal number is reached.
IRC2 IRC1 IRC0
0 0 0 zero wait states
0 X 1 illegal
1 1 X illegal
1 0 0 one wait state
1 0 1 two wait states
1 1 0 three wait states
1 1 1 infinite
Load CCB2
Setting this bit causes CCB2 to be read.
Address:
Reset State:
WDE BW1
Function
FF201AH
XXH
0
IRC2 LDCCB2
14-9