Design Considerations; System Bus Ac Timing Specifications - Intel 8XC196NT User Manual

14.8.5 Design Considerations

In all bus timing modes, for 16-bit bus-width operation, latch the upper and lower address/data
lines. In modes 1 and 2, for 8-bit bus-width operation, also latch the upper and lower address/data
lines; the upper address lines are not driven throughout the entire bus cycle (see Figures 14-23
and 14-24). In modes 0 and 3, for 8-bit bus-width operation, latch only the lower address/data
lines. In these modes, it is not necessary to latch the upper address lines because these lines are
driven throughout the entire bus cycle.

14.9 SYSTEM BUS AC TIMING SPECIFICATIONS

Refer to the latest data sheet for the AC timings to make sure your system meets specifications.
The major external bus timing specifications are shown in Figure 14-25.
XTAL1
CLKOUT
T
ALE/ADV#
RD#
BUS
(Read Cycle)
T
WR#
BUS
(Write Cycle)
BHE#, INST
AD15:8
(8-bit Mode)
A19:16
T
OSC
T
CLCL
T
LLCH
CLLH
T
LHLH
T
LHLL
T
LLRL
T
RLAZ
T
AVLL
T
LLAX
Address Out
AVDV
T
LLWL
Address Out
Valid
Address Out
Extended Address Out
Figure 14-25. System Bus Timing
INTERFACING WITH EXTERNAL MEMORY
T
T
CHCL
XHCH
T
RHLH
T
RLRH
T
RHDZ
T
RLDV
Data In
T
T
WHLH
WLWH
T
T
WHQX
QVWH
Data Out Address Out
T , T
WHBX RHBX
T , T
WHAX RHAX
A0295-02
14-39