Demultiplexed Bus Timings - Intel 8XC196NT User Manual

8XC196NT USER'S MANUAL
READ_DATA:
LDB TEMPW, [MAILBOX]
STB TEMPW, P3_REG[0]
POPA
RET
END
9.4.1.3

Demultiplexed Bus Timings

The master processor performs two bus cycles for each byte written and three bus cycles for each
byte read. For the slave device, only five bytes are used (two bytes for the pointer to the open
memory window, two bytes for the temporary storage register, and one byte for the base address).
A read requires 91 state times (9.1 µs at 20 MHz) and a write requires 86 state times (8.6 µs at 20
MHz). These times do not include interrupt latency (see "Interrupt Latency" on page 5-7). Figure
9-4 shows relative timing relationships. Consult the datasheet for actual timing specifications.
SLPCS#
SLPALE
(Note 1)
SLPRD#
SLP7:0/
P3.7:0
SLPWR#
SLPINT
Notes:
1. Connect to master's A1 signal.
2. Rising edge associated with either
– Read ready (write to P3_REG)
– Write complete (read of P3_PIN)
Figure 9-4. Standard Slave Mode Timings (Demultiplexed Bus)
9-10
; get data to write to P3_REG
; write SLP_CMD+400H data to P3_REG
Data
(Note 2)
A0307-02