Table of Contents
Advertisement
2.3.4
Memory Controller
The RALU communicates with all memory, except the register file and peripheral SFRs, through
the memory controller. (It communicates with the upper register file through the memory control-
ler except when windowing is used; see Chapter 4, "Memory Partitions,") The memory controller
contains the prefetch queue, the slave program counter (slave PC), address and data registers, and
the bus controller.
The bus controller drives the memory bus, which consists of an internal memory bus and the ex-
ternal address/data bus. The bus controller receives memory-access requests from either the
RALU or the prefetch queue; queue requests always have priority. This queue is transparent to
the RALU and your software.
When using a logic analyzer to debug code, remember that instructions are
preloaded into the prefetch queue and are not necessarily executed
immediately after they are fetched.
When the bus controller receives a request from the queue, it fetches the code from the address
contained in the slave PC. The slave PC increases execution speed because the next instruction
byte is available immediately and the processor need not wait for the master PC to send the ad-
dress to the memory controller. If a jump, interrupt, call, or return changes the address sequence,
the master PC loads the new address into the slave PC, then the CPU flushes the queue and con-
tinues processing.
The extended program counter (EPC) is an extension of the slave PC. The EPC generates the up-
per eight address bits for extended code fetches and outputs them on the extended addressing port
(EPORT). Because only four EPORT pins are implemented, only the lower four address bits are
available. (See Chapter 4, "Memory Partitions," for additional information.)
2.3.5
Interrupt Service
The device's flexible interrupt-handling system has two main components: the programmable in-
terrupt controller and the peripheral transaction server (PTS). The programmable interrupt con-
troller has a hardware priority scheme that can be modified by your software. Interrupts that go
through the interrupt controller are serviced by interrupt service routines that you provide. The
peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides high-
speed, low-overhead interrupt handling. You can configure most interrupts (except NMI, trap,
and unimplemented opcode) to be serviced by the PTS instead of the interrupt controller.
ARCHITECTURAL OVERVIEW
NOTE
2-5
Advertisement
Table of Contents
