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5.3.3
Multiplexed Interrupt Sources
The EPAx interrupt is generated by a group of multiplexed interrupt sources. The EPA4–9 and
COMP0–1 event interrupts, the EPA0–9 overrun interrupts, and the timer 1 and timer 2 over-
flow/underflow interrupts are multiplexed into EPAx. Generally, PTS interrupt service is not use-
ful for multiplexed interrupts because the PTS cannot readily determine the interrupt source. Your
interrupt service routine should read the EPA_PEND or EPA_PEND1 register to determine the
source of the interrupt and to ensure that no additional interrupts are pending before executing the
return instruction. Chapter 10, "Event Processor Array (EPA)," discusses the EPA interrupts in
detail.
5.3.4
End-of-PTS Interrupts
When the PTSCOUNT register decrements to zero at the end of a single transfer, block transfer,
or A/D scan routine, hardware clears the corresponding bit in the PTSSEL register, which disables
PTS service for that interrupt. It also sets the corresponding PTSSRV bit, requesting an end-of-
PTS interrupt. An end-of-PTS interrupt has the same priority as a corresponding standard inter-
rupt. The interrupt controller processes it with an interrupt service routine that is stored in the
memory location pointed to by the standard interrupt vector. For example, the PTS services the
SIO transmit interrupt if PTSSEL.11 is set. The interrupt vectors through FF2056H, but the cor-
responding end-of-PTS interrupt vectors through FF2036H, the standard SIO transmit interrupt
vector. When the end-of-PTS interrupt vectors to the interrupt service routine, hardware clears the
PTSSRV bit. The end-of-PTS interrupt service routine should reinitialize the PTSCB, if required,
and set the appropriate PTSSEL bit to re-enable PTS interrupt service.
5.4
INTERRUPT LATENCY
Interrupt latency is the total delay between the time that the interrupt request is generated (not
acknowledged) and the time that the device begins executing either the standard interrupt service
routine or the PTS interrupt service routine. A delay occurs between the time that the interrupt
request is detected and the time that it is acknowledged. An interrupt request is acknowledged
when the current instruction finishes executing. If the interrupt request occurs during one of the
last four state times of the instruction, it may not be acknowledged until after the next instruction
finishes. This additional delay occurs because instructions are prefetched and prepared a few state
times before they are executed. Thus, the maximum delay between interrupt request and ac-
knowledgment is four state times plus the execution time of the next instruction.
When a standard interrupt request is acknowledged, the hardware clears the interrupt pending bit
and forces a call to the address contained in the corresponding interrupt vector. When a PTS in-
terrupt request is acknowledged, the hardware immediately vectors to the PTSCB and begins ex-
ecuting the PTS routine.
STANDARD AND PTS INTERRUPTS
5-7
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