Enabling The Slave Port Interrupts; Determining Slave Port Status; Using Status Bits To Synchronize Master And Slave - Intel 8XC196NT User Manual

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8XC196NT USER'S MANUAL
9.5.2

Enabling the Slave Port Interrupts

The master can generate three interrupt requests: command buffer full (CBF), output buffer emp-
ty (OBE), and input buffer full (IBF). The CBF interrupt is used in standard slave mode; the OBE
and IBF interrupts are used in shared memory mode. To enable an interrupt, set the corresponding
bit in the interrupt mask register (Table 9-2 on page 9-4).
9.6

DETERMINING SLAVE PORT STATUS

The master can determine the status of the slave port by reading the SLP_STAT register (Figure
9-7). It can also read the interrupt pending registers (Table 9-2 on page 9-4) to determine the status
of the interrupts.
9.7

USING STATUS BITS TO SYNCHRONIZE MASTER AND SLAVE

The status bits in the SLP_STAT register can be used to synchronize the master with the slave.
Because synchronization of the status bits is not monitored by the status flags, it is more difficult
for the master to monitor. Software must ensure data integrity throughout the operation. Two
techniques are recommended — a double read or a software flag.
If the master processor is fast enough to read SLP_STAT twice before the contents change, the
master can compare the readings from before and after the data fetch. If the readings are identical,
the data is guaranteed correct.
In standard slave mode, the slave can use bit 7 of SLP_STAT to indicate valid data. To update the
status, the slave performs the following sequence:
Clear the flag bit (bit 7) without changing the other four status bits.
Update the status bits (SLP_STAT.6:3).
Set the flag bit (bit 7) without changing the other four status bits.
9-16

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