Intel 8XC196NT User Manual page 423

8XC196NT USER'S MANUAL
Mnemonic
DIVU DIVIDE WORDS, UNSIGNED. Divides the
contents of the destination double-word
operand by the contents of the source word
operand, using unsigned arithmetic. It stores
the quotient into the low-order word (i.e., the
word with the lower address) of the
destination operand and the remainder into
the high-order word. The following two
statements are performed concurrently.
(low word DEST)
(high word DEST)
Z
—
DIVUB DIVIDE BYTES, UNSIGNED. This instruction
divides the contents of the destination word
operand by the contents of the source byte
operand, using unsigned arithmetic. It stores
the quotient into the low-order byte (i.e., the
byte with the lower address) of the
destination operand and the remainder into
the high-order byte. The following two
statements are performed concurrently.
(low byte DEST)
(high byte DEST)
Z
—
DJNZ DECREMENT AND JUMP IF NOT ZERO.
Decrements the value of the byte operand by
1. If the result is 0, control passes to the next
sequential instruction. If the result is not 0,
the instruction adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –128 to +127.
(COUNT)
if (COUNT)
←
PC
end_if
Z
—
A-14
Table A-6. Instruction Set (Continued)
Operation
←
(DEST) / (SRC)
←
(DEST) MOD (SRC)
PSW Flag Settings
N C V VT
↑
— —
←
(DEST) / (SRC)
←
(DEST) MOD (SRC)
PSW Flag Settings
N C V VT
↑
— —
←
(COUNT) –1
≠
0 then
PC + 8-bit disp
PSW Flag Settings
N C V VT
— — — —
Instruction Format
DEST, SRC
DIVU lreg, waop
(100011aa) (waop) (lreg)
ST
—
DEST, SRC
DIVUB wreg, baop
(100111aa) (baop) (wreg)
ST
—
DJNZ breg,cadd
(11100000) (breg) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
ST
—