Intel 8XC196NT User Manual page 528

INT_PEND
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
IBF OBE
Bit
Number
7:0 Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
IBF
OBE
AD
EPA0
EPA1
EPA2
EPA3
†
EPA x
†
EPA 4–9 capture/compare channel events, EPA 0–1 compare channel events, EPA 0–9
capture/compare overruns, and timer overflows can generate this multiplexed interrupt.
The EPA mask and pending registers decode the EPA x interrupt. Write the EPA mask
registers to enable the interrupt sources; read the EPA pending registers to determine
which source caused the interrupt.
AD EPA0
Function
Slave Port Input Buffer Full
Slave Port Output Buffer Empty
A/D Conversion Complete
EPA Capture/Compare Channel 0
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 3
Multiplexed EPA
Address:
Reset State:
EPA1 EPA2
Standard Vector
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2004H
FF2002H
FF2000H
REGISTERS
INT_PEND
0009H
00H
0
EPA x
EPA3
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