Intel 8XC196NT User Manual page 507

8XC196NT USER'S MANUAL
CCR1
CCR1
The chip configuration 1 (CCR1) register enables the watchdog timer and selects the bus timing
mode. Two of its bits combine with three bits of CCR0 to control wait states and bus width. Another bit
controls whether CCR2 is loaded.
7
MSEL1 MSEL0
Bit Bit
Number Mnemonic
7:6 MSEL1:0
5 0
4 1
3 WDE
2 BW1
1 IRC2
0 LDCCB2
C-12
0 1
External Access Timing Mode Select
These bits control the bus-timing modes.
MSEL1 MSEL0
0 0 standard mode plus one wait state
0 1 long read/write
1 0 long read/write with early address
1 1 standard mode
To guarantee device operation, write zero to this bit.
To guarantee device operation, write one to this bit.
Watchdog Timer Enable
Selects whether the watchdog timer is always enabled or enabled the
first time it is cleared.
1 = enabled first time it is cleared
0 = always enabled
Buswidth Control
This bit, along with the BW0 bit (CCR0.1), selects the bus width.
BW1 BW0
0 0 illegal
0 1 16-bit only
1 0 8-bit only
1 1 BUSWIDTH pin controlled
Ready Control
This bit, along with IRC0 (CCR0.4) and IRC1 (CCR0.5), limits the
number of wait states that can be inserted while the READY pin is held
low. Wait states are inserted into the bus cycle either until the READY
pin is pulled high or until this internal number is reached.
IRC2 IRC1 IRC0
0 0 0 zero wait states
0 X 1 illegal
0 1 X illegal
1 0 0 one wait state
1 0 1 two wait states
1 1 0 three wait states
1 1 1 infinite
Load CCB2
Setting this bit causes CCB2 to be read.
Address:
Reset State:
WDE BW1
Function
FF201AH
XXH
0
IRC2 LDCCB2