Intel 8XC196NT User Manual page 237

8XC196NT USER'S MANUAL
Table 10-2. EPA Control and Status Registers (Continued)
Mnemonic
EPA0_CON 1F60H
EPA1_CON 1F64H
EPA2_CON
1F68H
EPA3_CON 1F6CH
EPA4_CON 1F70H
EPA5_CON 1F74H
EPA6_CON 1F78H
EPA7_CON 1F7CH
EPA8_CON 1F80H
EPA9_CON 1F84H
EPA0_TIME
1F62H
EPA1_TIME 1F66H
EPA2_TIME 1F6AH
EPA3_TIME 1F6EH
EPA4_TIME 1F72H
EPA5_TIME 1F76H
EPA6_TIME 1F7AH
EPA7_TIME 1F7EH
EPA8_TIME 1F82H
EPA9_TIME 1F86H
EPAIPV 1FA8H
INT_MASK 0008H
INT_PEND 0009H
P1_DIR 1FD2H
P6_DIR 1FD3H
P1_MODE 1FD0H
P6_MODE 1FD1H
P1_PIN 1FD6H
P6_PIN 1FD7H
10-4
Address
EPA x Capture/Compare Control
These registers control the functions of the capture/compare
channels. EPA1_CON and EPA3_CON require an extra byte
because they contain an additional bit for PWM remap mode.
These two registers must be addressed as words; the others can
be addressed as bytes.
EPA x Capture/Compare Time
In capture mode, these registers contain the captured timer value.
In compare mode, these registers contain the time at which an
event is to occur. In capture mode, these registers are buffered to
allow two captures before an overrun occurs. However, they are
not buffered in compare mode.
EPA Interrupt Priority Vector Register
The lower four bits of this register contain a number from 01H to
14H corresponding to the highest priority active EPA x interrupt
source. This value, when used with the TIJMP instruction,
enables software to branch to the correct interrupt service routine
for the active interrupt.
Interrupt Mask
Five bits in this register enable and disable (mask) the individual
EPA0, EPA1, EPA2, and EPA3 interrupts and the multiplexed
EPA x interrupt. The EPA_MASK and EPA_MASK1 register bits
enable and disable the individual sources of the EPA x interrupt.
Interrupt Pending
Five bits in this register are set to indicate pending individual
interrupts EPA0, EPA1, EPA2, and EPA3, and the multiplexed
EPA x interrupt. The EPA_PEND and EPA_PEND1 register bits
indicate which source(s) of the EPA x interrupt are pending.
Port x Direction
Each bit of P x _DIR controls the direction of the corresponding pin.
Clearing a bit configures a pin as a complementary output; setting
a bit configures a pin as an input or open-drain output. (Open-
drain outputs require external pull-ups.)
Port x Mode
Each bit of P x _MODE controls whether the corresponding pin
functions as a standard I/O port pin or as a special-function
signal. Setting a bit configures a pin as a special-function signal;
clearing a bit configures a pin as a standard I/O port pin.
Port x Input
Each bit of P x _PIN reflects the current state of the corresponding
pin, regardless of the pin configuration.
Description