Table of Contents
Advertisement
8XC196NT USER'S MANUAL
12.2 APPLYING AND REMOVING POWER
When power is first applied to the device, RESET# must remain continuously low for at least one
state time after the power supply is within tolerance and the oscillator/clock has stabilized; oth-
erwise, operation might be unpredictable. Similarly, when powering down a system, RESET#
should be brought low before V
cation might occur. Carefully evaluate the possible effect of power-up and power-down sequenc-
es on a system.
12.3 NOISE PROTECTION TIPS
The fast rise and fall times of high-speed CMOS logic often produce noise spikes on the power
supply lines and outputs. To minimize noise, it is important to follow good design and board lay-
out techniques. We recommend liberal use of decoupling capacitors and transient absorbers. Add
0.01 µF bypass capacitors between V
ANGND to reduce noise (Figure 12-2). Place the capacitors as close to the device as possible.
Use the shortest possible path to connect V
†
+5 V
Power Source
† Use 0.01 µF bypass capacitors for maximum decoupling.
12-4
is removed; otherwise, an inadvertent write to an external lo-
CC
and each V
CC
lines to ground and each other.
SS
V
REF
8XC196 Device
ANGND
†
Digital
†
Ground
Plane
5 V
Return
Figure 12-2. Power and Return Connections
pin and a 1.0 µF capacitor between V
SS
+
1.0 µF
and
REF
+
V
REF
–
Analog
Ground
Plane
A0272-02
Advertisement
Table of Contents
